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NCP5316 Four/Five/Six-Phase Buck CPU Controller
The NCP5316 provides full-featured and flexible control for the latest high-performance CPUs. The IC can be programmed as a four-, five- or six-phase buck controller, and the per-phase switching frequency can be as high as 1.0 MHz. Combined with external gate drivers and power components, the controller implements a compact, highly integrated multi-phase buck converter. Enhanced V2TM control inherently compensates for variations in both line and load, and achieves current sharing between phases. This control scheme provides fast transient response, reducing the need for large banks of output capacitors and higher switching frequency. The controller meets VR(M)10.x specifications with all the required functions and protection features.
Features http://onsemi.com MARKING DIAGRAMS
48 1
NCP5316 AWLYYWW 48-PIN QFN, 7 y 7 MN SUFFIX CASE 485K (Bottom View)
* Switching Regulator Controller

* *
*
Programmable 4/5/6 Phase Operation Lossless Current Sensing Programmable Up to 1.0 MHz Switching Frequency Per Phase 0 to 100% Adjustment of Duty Cycle Programmable Adaptive Voltage Positioning Reduces Output Capacitor Requirements Programmable Soft Start Current Sharing Differential Current Sense Pins for Each Phase Current Sharing Within 10% Between Phases Protection Features Programmable Pulse-by-Pulse Current Limit for Each Phase "111110" and "111111" DAC Code Fault Latching Off Overvoltage Protection Programmable Latch Overcurrent Protection Undervoltage Lockout Reference Undervoltage Lockout MOSFET Driver Control through Driver-On Signal System Power Management 6-Bit DAC with 0.5% Tolerance Programmable Lower Power Good Threshold Power Good Output External Enable Control 3.3 V Reference Voltage Output
NCP5316 AWLYYWW
48
LQFP-48 FT SUFFIX CASE 932
1
A Location WL YY WW
= Assembly = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device NCP5316MNR2 NCP5316FTR2 Package 48-Pin QFN* LQFP-48* Shipping 2000 Tape & Reel 2000 Tape & Reel
*7 x 7 mm For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. 10
1
Publication Order Number NCP5316/D
NCP5316
CS3N
CS2N
48 47 46 45 44 43 42 41 40 39 38 37 VID5 VID0 VID1 VID2 VID3 VID4 LGND NC NC 1 2 3 4 5 6 7 8 9 36 CS1P 35 ROSC 34 VCC 33 GATE1 32 GATE2 31 GATE3 30 GATE4 29 GATE5 28 GATE6 27 GND 26 CS4P 25 CS4N 13 14 15 16 17 18 19 20 21 22 23 24 NC VFFB VFB NC CS6N DRVON CS5N CS6P ENABLE COMP CS5P SS
SGND 10 PWRGD 11 PWRLS 12
48-Pin QFN, Top View
VID5 VID0 VID1 VID2 VID3 VID4 LGND NC NC SGND PWRGD PWRLS
VCCL VREF IO IOF ILIM VDRP IPLIM CS3N CS3P CS2N CS2P CS1N 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
CS1N
CS3P
CS2P
VDRP
IPLIM
VCCL
VREF
IOF
ILIM
IO
1 2 3 4 5 6 7 8 9 10 11 12
CS1P ROSC VCC GATE1 GATE2 GATE3 GATE4 GATE5 GATE6 GND CS4P CS4N
DRVON SS ENABLE VFFB VFB COMP NC NC CS6N CS6P CS5N CS5P LQFP-48
Figure 1. Pin Connections
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2
ATX 12 V VOUT GND
12 V
5V
1
CO BST TG DRN
48 47 46 45 44 43 42 41 40 39 38 37
EN VS BG PGND
VCCL VREF IO IOF ILIM VDRP IPLIM CS3N CS3P CS2N CS2P CS1N
1
CO BST TG DRN
CPU_VSS_SENSE EN VS BG PGND
NCP5351
NCP5351 EN VS BG PGND
NCP5316
SSTART
1
13 14 15 16 17 18 19 20 21 22 23 24
DRVON SS ENABLE VFFB VFB COMP NC NC CS6N CS6P CS5N CS5P
CO BST TG DRN
SGND near socket VFFB connection
NCP5351 EN VS BG PGND
NCP5351 EN VS BG PGND
Figure 2. Application Diagram, 12 V to 0.8375 - 1.600 V Six-Phase Converter
NCP5351 EN VS BG PGND CO BST TG DRN
1
3.3 V
NCP5351
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NTC Thermistor near closest inductor CPU_VCC_SENSE
PWRGD
1 2 3 4 5 6 7 8 9 10 11 12
VID5 VID0 VID1 VID2 VID3 VID4 LGND NC NC SGND PWRGD PWRLS
CS1P ROSC VCC GATE1 GATE2 GATE3 GATE4 GATE5 GATE6 GND CS4P CS4N
36 35 34 33 32 31 30 29 28 27 26 25
ENABLE
CO BST TG DRN
VID5 VID0 VID1 VID2 VID3 VID4
NCP5316
1
CO BST TG DRN
1
3
NCP5316
MAXIMUM RATINGS
Rating Operating Junction Temperature Lead Temperature Soldering, Reflow (Note 1) Storage Temperature Range ESD Susceptibility: Human Body Model (HBM) Moisture Sensitivity Level (MSL), LQFP MSL, QFN qJA, LQFP qJA, QFN, Pad Soldered to PCB 1. 60 second maximum above 183C. Value 150 230 peak -65 to 150 2.0 1 2 52 34 Unit C C C kV - - C/W C/W
MAXIMUM RATINGS
Pin Number 15 1-6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28-33 34 35 36 37 38 39 40 Pin Symbol ENABLE VID0-VID5 LGND NC NC SGND PWRGD PWRLS DRVON SS VFFB VFB COMP NC NC CS6N CS6P CS5N CS5P CS4N CS4P GND GATE6-GATE1 VCC ROSC CS1P CS1N CS2P CS2N CS3P VMAX 18 V 18 V - NA NA 1.0 V 18 V 7.0 V 7.0 V 7.0 V 7.0 V 7.0 V 7.0 V NA NA 18 V 18 V 18 V 18 V 18 V 18 V - 18 V 18 V 7.0 V 18 V 18 V 18 V 18 V 18 V VMIN -0.3 V -0.3 V - NA NA -1.0 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V NA NA -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V - -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE 1.0 mA 1.0 mA 50 mA NA NA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA NA NA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 0.4 A, 1.0 ms, 100 mA DC 0.1 A, 1.0 ms, 25 mA DC - 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA ISINK 1.0 mA 1.0 mA - NA NA - 20 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA NA NA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA - 0.1 A, 1.0 ms, 25 mA DC 0.4 A, 1.0 ms, 100 mA DC 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA
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NCP5316
MAXIMUM RATINGS (continued)
Pin Number 41 42 43 44 45 46 47 48 Pin Symbol CS3N IPLIM VDRP ILIM IOF IO VREF VCCL VMAX 18 V 7.0 V 7.0 V 7.0 V 7.0 V 7.0 V 7.0 V 18 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 5.0 mA 5.0 mA - ISINK 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 50 mA
VOLTAGE IDENTIFICATION (VID)
VID Pins (0 = low, 1 = high) VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.1000 1.1125 1.1250 1.1375 1.1500 1.0746 1.0870 1.0995 1.1119 1.1244 VID Code*(V) 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 -0.5% 0.8134 0.8259 0.8383 0.8507 0.8632 0.8756 0.8880 0.9005 0.9129 0.9254 0.9378 0.9502 0.9627 0.9751 0.9875 1.0000 1.0124 1.0249 1.0373 1.0497 1.0622 OFF OFF 1.0800 1.0925 1.1050 1.1175 1.1300 1.0854 1.0980 1.1105 1.1231 1.1357 VOUT No Load (V) 0.8175 0.8300 0.8425 0.8550 0.8675 0.8800 0.8925 0.9050 0.9175 0.9300 0.9425 0.9550 0.9675 0.9800 0.9925 1.0050 1.0175 1.0300 1.0425 1.0550 1.0675 +0.5% 0.8216 0.8342 0.8467 0.8593 0.8718 0.8844 0.8970 0.9095 0.9221 0.9347 0.9472 0.9598 0.9723 0.9849 0.9975 1.0100 1.0226 1.0352 1.0477 1.0603 1.0728
*VID Code is for reference only. VOUT No Load is the input to the error amplifier.
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NCP5316
VOLTAGE IDENTIFICATION (VID) (continued)
VID Pins (0 = low, 1 = high) VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID Code*(V) 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 -0.5% 1.1368 1.1492 1.1617 1.1741 1.1865 1.1990 1.2114 1.2239 1.2363 1.2487 1.2612 1.2736 1.2860 1.2985 1.3109 1.3234 1.3358 1.3482 1.3607 1.3731 1.3855 1.3980 1.4104 1.4229 1.4353 1.4477 1.4602 1.4726 1.4850 1.4975 1.5099 1.5224 1.5348 1.5472 1.5597 1.5721 VOUT No Load (V) 1.1425 1.1550 1.1675 1.1800 1.1925 1.2050 1.2175 1.2300 1.2425 1.2550 1.2675 1.2800 1.2925 1.3050 1.3175 1.3300 1.3425 1.3550 1.3675 1.3800 1.3925 1.4050 1.4175 1.4300 1.4425 1.4550 1.4675 1.4800 1.4925 1.5050 1.5175 1.5300 1.5425 1.5550 1.5675 1.5800 +0.5% 1.1482 1.1608 1.1733 1.1859 1.1985 1.2110 1.2236 1.2362 1.2487 1.2613 1.2738 1.2864 1.2990 1.3115 1.3241 1.3367 1.3492 1.3618 1.3743 1.3869 1.3995 1.4120 1.4246 1.4372 1.4497 1.4623 1.4748 1.4874 1.5000 1.5125 1.5251 1.5377 1.5502 1.5628 1.5753 1.5879
*VID Code is for reference only. VOUT No Load is the input to the error amplifier.
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NCP5316
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; VCCL = VCC = 12 V; CGATEx = 100 pF, CCOMP = 0.01 mF, CSS = 0.1 mF, CVCC = 0.1 mF, RROSC = 32.4 kW, V(ILIM) = 3.3 V, V(IPLIM) = 3.3 V, unless otherwise noted)
Characteristic VID Inputs Input Threshold VID Pin Current SGND Bias Current SGND Voltage Compliance Range Power Good Upper Threshold Offset from VOUT No Load Lower Threshold Constant Output Low Voltage Delay Overvoltage Protection VID OVP Threshold above VID Enable Input Start Threshold Stop Threshold Input Pull-Up Voltage Input Pull-Up Resistance Voltage Feedback Error Amplifier VFB Bias Current COMP Source Current COMP Sink Current Transconductance Open Loop DC Gain Unity Gain Bandwidth PSRR @ 1.0 kHz COMP Max Voltage COMP Min Voltage PWM Comparators Minimum Pulse Width Measured from CSxP to GATEx, VFB = CSxN = 0.5, COMP = 0.5 V, 60 mV step between CSxP and CSxN; Measure at GATEx = 1.0 V Measured from CSxN to GATEx, COMP = 2.1 V, CSxP = CSxN = 0.5 V, CSxN stepped from 1.2 V to 2.0 V CSxP = CSxN = VFFB = 0, Measure Vcomp when GATEx switch high 50% duty cycle DRVON floating - DRVON = 1.5 V, ENABLE = 0 V, R = 1.5 V/I(DRVON) DRVON = 1.5 V 0 mA < I(VREF) < 1.0 mA Measure GATEx, IGATEx = 1.0 mA - 40 100 ns VFB = 0 V VFB = 1.6 V Note 2 Note 2 CCOMP = 30 pF - - COMP = 0.5 V to 2.0 V - - 40 40 1.1 72 - - 2.9 - 0.1 70 70 1.3 80 4.0 60 3 50 1.0 100 100 1.5 - - - - 150 mA mA mA mmho dB MHz dB V mV Gates switching, SS high Gates not switching, SS low 1.0 MW to GND - 0.8 - 2.7 7.0 - - 2.8 10 - 0.4 3.3 20 V V V kW - 190 200 250 mV IPWRGD = 4.0 mA VFFB low to PWRGD low - PWRLS/VOUT No Load 85 0.475 - 50 100 0.500 0.15 250 115 0.525 0.40 600 mV V/V V ms VID5, VID4, VID3, VID2, VID1, VID0 VID5, VID4, VID3, VID2, VID1, VID0 = 0 V SGND < 300 mV, All DAC Codes - 400 - 10 -200 - - 20 - 800 1.0 40 300 mV mA mA mV Test Conditions Min Typ Max Unit
Transient Response Time
-
40
60
ns
Channel Start-Up Offset Artificial Ramp Amplitude MOSFET Driver Enable (DRVON) Output High Output Low Pull-Down Resistance Source Current VREF Output Voltage GATES High Voltage
0.35 - 2.3 - 35 1 3.25 2.25
0.6 100 - - 70 4 3.3 2.70
0.75 - - 0.2 140 6.5 3.35 3.00
V mV V V kW mA V V
2. Guaranteed by design, not tested in production.
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NCP5316
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; VCCL = VCC = 12 V; CGATEx = 100 pF, CCOMP = 0.01 mF, CSS = 0.1 mF, CVCC = 0.1 mF, RROSC = 32.4 kW, V(ILIM) = 3.3 V, V(IPLIM) = 3.3 V, unless otherwise noted)
Characteristic GATES Low Voltage Rise Time GATE Fall Time GATE Oscillator Switching Frequency ROSC = 32.4 k, 4-Phase mode ROSC = 32.4 k, 5-Phase mode ROSC = 32.4 k, 6-Phase mode - - CS6P = CS6N = VCC CS3P = CS3N = CS6P = CS6N = VCC VCC - (CSxP = CSxN) CSxP = CSxN, VFB = COMP, Measure VDRP - COMP CSxP - CSxN = 80 mV, VFB = COMP, Measure VDRP - COMP, VDRP = 1.0 V CSxP - CSxN = 0 mV, VFB = COMP, VDRP = 2.0 V CSxP - CSxN = 80 mV, VFB = COMP, VDRP = 0.5 V VCCL = 10 V VCCL = 7.0 V VCCL = 10 V CSxN = CSxP = 0 V CSxN = CSxP = 0 V CSxN = 0 V, CSxP = 80 mV, Measure V(COMP) when GATEx switches high - IO/(CSxP - CSxN), ILIM = 0.6 V, GATEx not switching - - - ILIM = 0 V IOF = 0 V IPLIM = 0 V - Note 2 COMP = 0.3 V (no switching) SS charging, GATEx switching GATEx not switching, SS & COMP discharging Start - Stop 450 520 550 0.95 - - - 500 -15 2.3 1.0 0.2 525 620 650 1.0 60 72 90 - - 2.55 1.5 0.4 600 720 750 1.05 - - - - 15 2.75 14 0.6 kHz kHz kHz V deg deg deg mV mV V/V mA mA Measure GATEx, IGATEx = 1.0 mA 0.8 V < GATEx < 2.0 V, VCC = 10 V 2.0 V > GATEx > 0.8 V, VCC = 10 V - - - 0.1 2.5 5.0 0.7 10 10 V ns ns Test Conditions Min Typ Max Unit
ROSC Voltage Phase Delay, 6 Phases Phase Delay, 5 Phases Phase Delay, 4 Phases Phase Disable Threshold Adaptive Voltage Positioning VDRP Output Voltage to DACOUT Offset Current Sense Amplifier to VDRP Gain VDRP Source Current VDRP Sink Current Soft Start Charge Current Discharge Current COMP Pull-Down Current CSxP Input Bias Current CSxN Input Bias Current Current Sense Amp to PWM Gain Current Sense Amp to PWM Bandwidth Current Sense Amp to IO Gain Current Sense Amp to IO Bandwidth IO Source Current IO Sink Current ILIM Input Bias Current IOF Input Bias Current IPLIM Input Bias Current Current Sense Amp to Pulse-by-Pulse Current Limit Comparator Gain Current Sense Common Mode Input Range General Electrical Specifications VCC Operating Current UVLO Start Threshold UVLO Stop Threshold UVLO Hysteresis
30 90 0.2 - - - - 3.85 - 4.0 0.5 - - - 8.0 0 - 8.5 7.5 0.8
40 120 0.9 0.1 0.1 3.0 7.0 4.2 1.0 10 0.9 0.1 0.1 0.1 9.5 - 36 9.0 8.0 1.0
50 150 2.1 1.0 1.0 - - 4.4 - - 1.5 1.0 1.0 1.0 11 2.0 40 9.5 8.5 1.2
mA mA mA mA mA V/V MHz V/V MHz mA mA mA mA mA V/V V mA V V V
Current Sensing and Overcurrent Protection
2. Guaranteed by design, not tested in production.
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NCP5316
PIN DESCRIPTION
Pin No. 1-6 7 Pin Symbol VID0-VID5 LGND NC Pin Name DAC VID Inputs Logic Ground No Connect Description VID-compatible logic input used to program the converter output voltage. All high on VID0-VID4 generates fault. IC analog ground; connected to IC substrate. For factory test only. Let these pins float.
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8, 9, 19, 20 10 11 SGND Remote Sense Ground Power Good Output Power Good Sense Drive Enable Ground connection for DAC and error amplifier. Provides remote sensing of load ground. PWRGD PWRLS Open collector output goes high when the converter output is in regulation. Voltage sensing pin for Power Good lower threshold. 12 13 DRVON Logic high output enables MOSFET drivers, and logic low turns all MOSFETs off through MOSFET drivers. Pulled to ground through internal 70 kW resistor. 14 15 SS Soft Start Enable A capacitor between this pin and ground programs the soft start time. A voltage less than the threshold puts the IC in Fault Mode, discharging SS. Connect to system VIDPWRGD signal to control powerup sequencing. Hysteresis is provided to prevent chatter. ENABLE 16 17 18 VFFB VFB Fast Voltage Feedback Voltage Feedback Error Amp Output Input of PWM comparator for fast voltage feedback, and also the inputs of Power Good sense and overvoltage protection comparators Error amplifier inverting input. COMP Provides loop compensation and is clamped by SS during soft start and fault conditions. It is also the inverting input of PWM comparators. Inverting input to current sense amplifier #6, and Phase 6 disable pin. 21 22 23 24 25 26 27 CS6N CS6P Current Sense Reference Current Sense Input Non-inverting input to current sense amplifier #6, and Phase 6 disable pin. Inverting input to current sense amplifier #5. CS5N CS5P Current Sense Reference Current Sense Input Non-inverting input to current sense amplifier #5. Inverting input to current sense amplifier #4. CS4N CS4P GND Current Sense Reference Current Sense Input Ground Non-inverting input to current sense amplifier #4. Power supply return of Gate circuits. 28-33 34 35 36 37 38 39 40 41 42 43 GATE6-GATE1 VCC Channel Outputs PWM outputs to drive MOSFET driver ICs. Gate Power Supply Power Supply Input for Gate circuits. Must be tied to VCCL. ROSC Oscillator Frequency Adjust Current Sense Input Resistor to ground programs the oscillator frequency, as shown in Figure 5. Non-inverting input to current sense amplifier #1. Inverting input to current sense amplifier #1. CS1P CS1N CS2P Current Sense Reference Current Sense Input Non-inverting input to current sense amplifier #2. Inverting input to current sense amplifier #2. CS2N CS3P Current Sense Reference Current Sense Input Non-inverting input to current sense amplifier #3, and Phase 3 disable pin. Inverting input to current sense amplifier #3, and Phase 3 disable pin. Resistor divider from VREF to ground programs the threshold of pulse-by-pulse limit of each phase. CS3N IPLIM Current Sense Reference Pulse-by-Pulse Limit VDRP Output of Current Sense Amplifiers for Adaptive Voltage Positioning: "Droop" Pin The offset above DAC voltage is proportional to the sum of inductor current. A resistor from this pin to VFB programs the amount of Adaptive Voltage Positioning. Leave this pin open for no Adaptive Voltage Positioning.
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NCP5316
PIN DESCRIPTION (continued)
Pin No. 44 45 46 47 48 Pin Symbol ILIM Pin Name Total Current Limit Description Resistor divider between VREF and ground programs the average current limit.
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IOF IO Average Inductor Current Input Inductor Current Output Reference Connect a low pass filter from the 10 pin to the 10F pin to provide average inductor current information. Output of the sum of inductor current. 3.3 V reference voltage output. VREF VCCL Logic Power Supply Power supply input for IC logic. Must be tied to VCC.
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PWRGD
SS
VREF UVLO Comparator Fault Latch VCCL PWM Comparator Phase1 S Q PWM Latch 70k S RAMP1 Q
10 k
ENABLE
VCCL
-+
R Discharge Current R 200 mV PWM Comparator S RAMP2 Q OVP Comparator CO1F SET Dominant 9.0 V 8.0 V CO1 Pulse Current Comparator Charge Current
- +
0.8 V 0.4 V
-+
- Enable Comparator +
DRVON
+
+ -
RESET Dominant
- +
3.3 V Reference VREF Comparator
VCC GATE1
VREF
- + -+ - + - +
Phase2
+ -
VID = 11111x DAC Output 100 mV PWRGD Comparator R CO2 CO2F
3.0 V 2.9 V
PWM Latch S Q
VCC GATE2
DAC
+
+ -
PWM Comparator
VID5 VID0 VID1 VID2 VID3 VID4 SGND SET Dominant
RESET Dominant R
PWRLS 20 mV CO1 Delay RAMP3 CO3 CO3F
-+ +-
0.5 PWRGD Comparator
VCC Phase3 PWM Latch S Q GATE3
- + + -
0.6 V
CS1P
CO1 x3
CS1N
+ -
+ -
CO2
+ -
PWM Comparator RAMP4 CO4 CO4F Phase4
CS2P Error Amplifier
CO2 x3 +
-+ + - +-
Phase 3 Disable Comparator
RESET Dominant R
CO1F x 9.5 CO1F
+
- +
NCP5316
CS3N
+ -
CO3F + x 9.5 CO3F
-
CO4
+
-+ + -
CS3P
+ -
+ -
PWM Comparator Phase5 RAMP5 CO5 CO5F
RESET Dominant
CS5P IO Buffer AVP Buffer
CO5 x3 + CO5
-+
+ -
+ -
VCC - 0.5 V Current Source Generator Oscillator PWM Comparator Phase6 RAMP6
CS5N
- -+
x 1.4
RESET Dominant
CO6F + x 9.5 CO6F
-
IO ILIM IOF VDRP
1.0 V VFFB VFB
+ -
ROSC LGND COMP IPLIM
RESET Dominant
Figure 3. Block Diagram
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CO3 Module OC Comparator
11
VCC PWM Latch S Q GATE4
CS2N
-
CO2F + x 9.5 CO2F
-
+
- +
CS3P
CO3 x3
R
VCC PWM Latch S Q GATE5
CS4P
CO4 x3 +
CS4N
-
CO4F + x 9.5 CO4F
+
-
VCC - 0.5 V Phase 6 Disable Comparator CS6P
+
- +
R
+ -
CO6
CO5F x 9.5 CO5F
VCC PWM Latch
-+
x 0.85
CS6P
CO6 x3 +
Phase1 Ramp1 Phase2 Ramp2 Phase3 Ramp3 Phase4 Ramp4 Phase5 Ramp5 Phase6 Ramp6
+
+ - + -
CO6 CO6F
- +
S
Q
GATE6 GND R
CS6N
-
SS
VREF Fault
DRVON
COMP Fault
Fault Reset
UVLO Fault
Fault Latch
PWRGD Enable VOUT ILOAD Power-On Enabled Start Up Normal Operation Pulse-by-Pulse Current Limit Overcurrent Latch-Off Power-Off to Reset OC Fault Power-On Enabled Start Up
VCC
NCP5316
Figure 4. Operating Waveforms
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UVLO Power-Off to Reset OC Fault Power-On Enabled Start Up Overvoltage Power-Off
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TYPICAL PERFORMANCE CHARACTERISTICS
1000 4 Phases 6 Phases 5 Phases CURRENT SENSE AMP GAIN (V/V) 1000 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 0 10 20 30 40 TA (C) 50 60 70 80
FSW (kHz) 100 10
100 ROSC (kW)
Figure 5. ROSC (kW) vs. fSW (kHz)
Figure 6. Current Sense Amplifier to PWM Gain vs. TA
CURRENT SENSE TO VDRP GAIN (V/V)
2.65
9.80 9.75
2.60 IPLIM GAIN (V/V) 10 30
9.70 9.65 9.60 9.55 9.50 9.45
2.55
2.50
2.45
0
20
40 TA (C)
50
60
70
80
9.40
0
10
20
30
40 TA (C)
50
60
70
80
Figure 7. Current Sense to VDRP Gain vs. TA
4.40 4.35 IO GAIN (V/V) 4.30 4.25 4.20 4.15 4.10 0 10 20 30 40 TA (C) 50 60 70 80 120 115 RAMP AMPLITUDE (mV) 110 105 100 95 90 85 80 0 10
Figure 8. IPLIM Gain vs. TA
20
30
40 TA (C)
50
60
70
80
Figure 9. IO Gain vs. TA
Figure 10. Artificial Ramp Amplitude at 50% Duty Cycle vs. TA
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TYPICAL PERFORMANCE CHARACTERISTICS
DAC VARIATION FROM NOMINAL (%) 0.25 AVERAGE CHANNEL OFFSET (mV) 0 10 20 30 40 TA (C) 50 60 70 80 800 750 700 650 600 550 500 450 400 0 10 20 30 40 TA (C) 50 60 70 80
0
-0.25
Figure 11. DAC Output vs. TA
220 215 PWRGD DELAY (mS) THRESHOLD (mV) 210 205 200 195 190 0 10 20 30 40 TA (C) 50 60 70 80 255 250 245 240 235 230 225 0
Figure 12. Average Channel Offset vs. TA
10
20
30
40 TA (C)
50
60
70
80
Figure 13. OVP Latch Threshold vs. TA
Figure 14. PWRGD Delay vs. TA
44 SS CHARGE CURRENT (mA) 43 42 41 40 39 38 0 10 20 30 40 TA (C) 50 60 70 80 ICC (mA)
41 39 37 35 33 31 29 27 25 0 10 20 30 40 TA (C) 50 60 70 80
Figure 15. SS Charge Current vs. TA
Figure 16. ICC vs. TA
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APPLICATIONS INFORMATION
Overview
The NCP5316 DC/DC controller from ON Semiconductor was developed using the Enhanced V2 topology. Enhanced V2 combines the original V2 topology with peak current-mode control for fast transient response and current sensing capability. The addition of an internal PWM ramp and implementation of fast-feedback directly from Vcore has improved transient response and simplified design. This controller can be adjusted to operate as a four-, five- or six-phase controller, and can also be used in a one-, two- or three-phase system. Differential current sensing provides improved current sharing and easier layout. The NCP5316 includes Power Good (PWRGD), providing a highly integrated solution to simplify design, minimize circuit board area, and reduce overall system cost. Two advantages of a multi-phase converter over a single-phase converter are current sharing and increased effective output frequency. Current sharing allows the designer to use less inductance in each phase than would be required in a single-phase converter. The smaller inductor will produce larger ripple currents but the total per-phase power dissipation is reduced because the RMS current is lower. Transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. Increased apparent output frequency is desirable because the off- time and the ripple voltage of the multi-phase converter will be less than that of a single-phase converter.
Fixed Frequency Multi-Phase Control
In a multi-phase converter, multiple converters are connected in parallel and are switched on at different times. This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components.
The NCP5316 controller uses six-phase, fixed-frequency, Enhanced V2 architecture to measure and control currents in individual phases. In six-phase mode, each phase is delayed 60 from the previous phase. Normally, GATEx transitions to a high voltage at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the PWM comparator and bring GATEx low. Once GATEx goes low, it will remain low until the beginning of the next oscillator cycle. While GATEx is high, the Enhanced V2 loop will respond to line and load variations. On the other hand, once GATEx is low, the loop cannot respond until the beginning of the next PWM cycle. Therefore, constant frequency Enhanced V2 will typically respond to disturbances within the off-time of the converter. The Enhanced V2 architecture measures and adjusts the output current in each phase. An additional differential input (CSxN and CSxP) for inductor current information has been added to the V2 loop for each phase as shown in Figure 17. The triangular inductor current is measured differentially across RS, amplified by CSA and summed with the channel startup offset, the internal ramp and the output voltage at the non-inverting input of the PWM comparator. The purpose of the internal ramp is to compensate for propagation delays in the NCP5316. This provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation and PWM duty cycles above 50% without external slope compensation. As the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the PWM comparator rises and terminates the PWM cycle. If the inductor starts a cycle with higher current, the PWM cycle will terminate earlier providing negative feedback. The NCP5316 provides a differential current sense input (CSxN and CSxP) for each phase. Current sharing is accomplished by referencing all phases to the same COMP pin, so that a phase with a larger current signal will turn off earlier than a phase with a smaller current signal.
x = 1, 2, 3, 4, 5 or 6 SWNODE Lx RLx RSx CSxN VOUT (VCORE)
+
CSxP
+ CSA - VFFB
COx
Internal Ramp + - + - PWM COMP To PWM Latch Reset
VFB
"Fast-Feedback" Channel Connection Start-Up Offset - E.A. +
+
DAC COMP Out
Figure 17. Enhanced V2 Control Employing Resistive Current Sensing and Internal Ramp
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NCP5316
Enhanced V2 responds to disturbances in VCORE by employing both "slow" and "fast" voltage regulation. The internal error amplifier performs the slow regulation. Depending on the gain and frequency compensation set by the amplifier's external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in one or two PWM cycles. Fast voltage feedback is implemented by a direct connection from Vcore to the non-inverting pin of the PWM comparator via the summation with the inductor current, internal ramp and offset. A rapid increase in output current will produce a negative offset at Vcore and at the output of the summer. This will cause the PWM duty cycle to increase almost instantly. Fast feedback will typically adjust the PWM duty cycle in one PWM cycle. As shown in Figure 17, an internal ramp (100 mV at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the PWM comparator. This additional ramp compensates for propagation time delays from the current sense amplifier (CSA), the PWM comparator and the MOSFET gate drivers. As a result, the minimum ON time of the controller is reduced and lower duty-cycles may be achieved at higher frequencies. Also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the RCSxCCSx time constant of the feedback components from VCORE to the CSx pin. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. When the average output current is zero, the COMP pin will be:
VCOMP + VOUT @ 0 A ) Channel_Startup_Offset ) Int_Ramp ) GCSA @ Ext_Ramp 2
or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as:
DV + RS @ GCSA @ DIOUT
The single-phase power stage output impedance is:
Single Stage Impedance + DVOUT DIOUT + RS @ GCSA
The total output impedance will be the single stage impedance divided by the number of phases in operation. The output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the COMP pin. The peak output current can be calculated from:
IOUT,PEAK + (VCOMP * VOUT * Offset) (RS @ GCSA)
Int_Ramp is the "partial" internal ramp value at the corresponding duty cycle, Ext_Ramp is the peak-to-peak external steady-state ramp at 0 A, GCSA is the current sense amplifier gain (3.0 V/V) and the channel startup offset is 0.60 V. The magnitude of the Ext_Ramp can be calculated from:
Ext_Ramp + D @ (VIN * VOUT) (RCSx @ CCSx @ fSW)
Figure 18 shows the step response of the COMP pin at a fixed level. Before T1, the converter is in normal steady-state operation. The inductor current provides a portion of the PWM ramp through the current sense amplifier. The PWM cycle ends when the sum of the current ramp, the "partial" internal ramp voltage signal and offset exceed the level of the COMP pin. At T1, the output current increases and the output voltage sags. The next PWM cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the VFB pin and the cycle ends at T2. After T2, the output voltage remains lower than at light load and the average current signal level (CSx output) is raised so that the sum of the current and voltage signal is the same as with the original load. In a closed loop system, the COMP pin would move higher to restore the output voltage to the original level.
SWNODE
VFB (VOUT)
For example, if VOUT at 0 A is set to 1.480 V with AVP and the input voltage is 12.0 V, the duty cycle (D) will be 1.480/12.0 or 12.3%. Int_Ramp will be 100 mV/50% 12.3% = 25 mV. Realistic values for RCSx, CCSx and fSW are 10 kW, 0.015 mF and 650 kHz. Using these and the previously mentioned formula, Ext_Ramp will be 15.0 mV.
VCOMP + 1.480 V ) 0.60 V ) 25 mV ) 2.65 V V @ 15.0 mV 2 + 2.125 Vdc.
Internal Ramp CSA Out COMP-Offset CSA Out + Ramp + CSREF
T1
T2
If the COMP pin is held steady and the inductor current changes, there must also be a change in the output voltage,
Figure 18. Open Loop Operation
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NCP5316
SWNODE Lx RLx VOUT (VCORE) RCSx x = 1, 2, 3, 4, 5 or 6 CSxP CCSx CSxN VFFB + CSA - COx
Internal Ramp + - + - PWM COMP To PWM Latch Reset
+
"Fast-Feedback" Connection VFB DAC Out COMP
+
- E.A. +
Channel Start-Up Offset
Figure 19. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp Inductive Current Sensing
For lossless sensing, current can be measured across the inductor as shown in Figure 19. In the diagram, L is the output inductance and RL is the inherent inductor resistance. To compensate the current sense signal, the values of RCSx and CCSx are chosen so that L/RL = RCSx CCSx. If this criteria is met, the current sense signal should be the same shape as the inductor current and the voltage signal at CSx will represent the instantaneous value of inductor current. Also, the circuit can be analyzed as if a sense resistor of value RL was used. When choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0.39% per C. The increase in winding resistance at higher temperatures should be considered when setting the threshold. If a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in Figure 17.
Current Sharing Accuracy
Current Sense Amplifier (CSA) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. The worst case CSA input mismatch is 10 mV and will typically be within 4.0 mV. The difference in peak currents between phases will be the CSA input mismatch divided by the current sense resistance. If all current sense components are of equal resistance, a 3.0 mV mismatch with a 2.0 mW sense resistance will produce a 1.5 A difference in current between phases.
External Ramp Size and Current Sensing
Printed circuit board (PCB) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. For accurate current sharing, the current sense inputs should sense the current at relatively the same points for each phase. In some cases, especially with inductive sensing, resistance of the PCB can be useful for increasing the current sense resistance. The total current sense resistance used for calculations must include any PCB trace resistance that carries inductor current between the CSxP input and the CSxN input.
The internal ramp allows flexibility in setting the current sense time constant. Typically, the current sense RCSx CCSx time constant should be equal to or slightly slower than the inductor's time constant. If RC is chosen to be smaller (faster) than L/RL, the AC or transient portion of the current sensing signal will be scaled larger than the DC portion. This will provide a larger steady-state ramp, but circuit performance will be affected and must be evaluated carefully. The current signal will overshoot during transients and settle at the rate determined by RCSx CCSx. It will eventually settle to the correct DC level, but the error will decay with the time constant of RCSx CCSx. If this error is excessive, it will affect transient response, adaptive positioning and current limit. During a positive current transient, the COMP pin will be required to undershoot in response to the current signal in order to maintain the output voltage. Similarly, the VDRP signal will overshoot which will produce too much transient droop in the output voltage. The single-phase pulse-by-pulse overcurrent protection will trip earlier than it would if compensated correctly and hiccup-mode current limit will have a lower threshold for fast rising step loads than for slowly rising output currents.
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NCP5316
Transient Response and Adaptive Voltage Positioning
For applications with fast transient currents, the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. Adaptive voltage positioning can reduce peak-peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. Similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. For low current applications, a droop resistor can provide fast, accurate adaptive positioning. However, at high currents, the loss in a droop resistor becomes excessive. For example, a 50 A converter with a 1 mW resistor would provide a 50 mV change in output voltage between no load and full load and would dissipate 2.5 W. Lossless adaptive voltage positioning (AVP) is an alternative to using a droop resistor, but it must respond to changes in load current. Figure 20 shows how AVP works. The waveform labeled "normal" shows a converter without AVP. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) AVP, the peak-to-peak excursions are cut in half. In the slow AVP waveform, the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. The controller can be configured to adjust the output voltage based on the output current of the converter. (Refer to the application diagram in Figure 2). The no-load positioning is now set internally to VID - 20 mV, reducing the potential error due to resistor and bias current mismatches. In order to realize the AVP function, a resistor divider network is connected between VFB, VDRP and VOUT. During no-load conditions, the VDRP pin is at the same voltage as the VFB pin. As the output current increases, the VDRP pin voltage increases proportionally. This drives the VFB voltage higher, causing VOUT to "droop" according to a loadline set by the resistor divider network. The response during the first few microseconds of a load transient is controlled primarily by power stage output
impedance, and by the ESR and ESL of the output filter. The transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. If the ramp size is too large or the error amp too slow, there will be a long transition to the final voltage after a transient. This will be most apparent with low capacitance output filters.
Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits
Figure 20. Adaptive Voltage Positioning Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of the normal operation of the Enhanced V2 control topology with synchronous rectifiers. The control loop responds to an overvoltage condition within 40 ns, causing the GATEx output to shut off. The (external) MOSFET driver should react normally to turn off the top MOSFET and turn on the bottom MOSFET. This results in a "crowbar" action to clamp the output voltage and prevent damage to the load. The regulator will remain in this state until the fault latch is reset by cycling power at the VCC pin. If the voltage at the VFFB pin exceeds 200 mV above the VID voltage, the converter will latch off.
Power Good
According to the latest specifications, the Power Good (PWRGD) signal must be asserted when the output voltage is within a window defined by the VID code, as shown in Figure 21. The PWRLS pin is provided to allow the PWRGD comparators to accurately sense the output voltage. The effect of the PWRGD lower threshold can be modified using a resistor divider from the output to PWRLS to ground, as shown in Figure 22.
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NCP5316
PWRGD PWRGD low HIGH
LOW
-2.6% +2.6%
VLOWER
Figure 21. PWRGD Assertion Window
Since the internally-set thresholds for PWRLS are VOUT No Load /2 for the lower threshold and VOUT No Load + 100 mV for the upper threshold, a simple equation can be provided to assist the designer in selecting a resistor divider to provide the desired PWRGD performance.
V NoLoad R1 ) R2 VLOWER + OUT @ 2 R1 VUPPER + VOUT NoLoad ) 100 mV
The logic circuitry inside the chip sets PWRGD low only after a delay period has been passed. A "power bad" event does not cause PWRGD to go low unless it is sustained through the delay time of 250 ms. If the anomaly disappears before the end of the delay, the PWRGD output will never be set low. In order to use the PWRGD pin as specified, the user is advised to connect external resistors as necessary to limit the current into this pin to 4 mA or less.
Undervoltage Lockout
The NCP5316 includes an undervoltage lockout circuit. This circuit keeps the IC's output drivers low until VCC applied to the IC reaches 9 V. The GATE outputs are disabled when VCC drops below 8 V.
Soft Start
At initial power-up, both SS and COMP voltages are zero. The total SS capacitance will begin to charge with a current of 40 mA. The error amplifier directly charges the COMP capacitance. An internal clamp ensures that the COMP pin voltage will always be less than the voltage at the SS pin, ensuring proper start-up behavior. All GATE outputs are held low until the COMP voltage reaches 0.6 V. Once this threshold is reached, the GATE outputs are released to operate normally.
EEE EEE CCC CCC CCC CCC
-5.0% +5.0%
PWRGD high
PWRGD low
VOUT R1 PWRLS
EEE EEE CCC CCC CCC CCC
VOUT
R2
VID + 80 mV
Figure 22. Adjusting the PWRGD Threshold Current Limit
Two levels of over-current protection are provided. First, if the absolute value of the voltage between the Current Sense pins (CSxN and CSxP) exceeds the voltage at the IPLIM pin (Single Pulse Current Limit), the PWM comparator is turned off. This provides fast peak current protection for individual phases. Second, the individual phase currents are summed and externally low-pass filtered to compare an averaged current signal to a user adjustable voltage on the ILIM pin. If the ILIM voltage is exceeded, the fault latch trips and the converter is latched off. VCC must be recycled to reset the latch.
Fault Protection Logic
The NCP5316 includes fault protection circuitry to prevent harmful modes of operation from occurring. The fault logic is described in Table 1.
Gate Outputs
The NCP5316 is designed to operate with external gate drivers. Accordingly, the gate outputs are capable of driving a 100 pF load with typical rise and fall times of 5 ns.
Digital to Analog Converter (DAC)
The output voltage of the NCP5316 is set by means of a 6-bit, 0.5% DAC. The VID pins must be pulled high externally. A 1 kW pullup to a maximum of 3.3 V is recommended to meet Intel specifications. To ensure valid logic signals, the designer should ensure at least 800 mV will be present at the IC for a logic high. The output of the DAC is described in the Electrical Characteristics section of the data sheet. These outputs are consistent with VR 10.x and processor specifications. The DAC output is equal to the VID code specification minus 20 mV. The latest VR and processor specifications require a power supply to turn its output off in the event of a 11111X VID code. When the DAC sees such a code, the GATE pins stop switching and go low. This condition is described in Table 1.
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NCP5316
Table 1. Description of Fault Logic
Results Faults Overvoltage Lockout Enable Low Module Overcurrent Limit DAC Code = 11111x VREF Undervoltage Lockout Phase Negative Overcurrent Limit Phase Overcurrent Limit PWRLS Out of Range Stop Switching Yes Yes Yes Yes Yes Yes Terminate Pulse No Depends on output voltage level Depends on output voltage level Depends on output voltage level Depends on output voltage level Depends on output voltage level Depends on output voltage level Low PWRGD Level Driver Enable High Low Low Low Low Low High High SS Characteristics -0.3 mA -0.3 mA -0.3 mA -0.3 mA -0.3 mA -0.3 mA Not Affected Not Affected Reset Method Power On Not Affected Power On Change VID Code Power On Power On Not Affected Not Affected
Adjusting the Number of Phases
2. Output Capacitor Selection
The NCP5316 was designed with a selectable-phase architecture. Designers may choose any number of phases up to six. The phase delay is automatically adjusted to match the number of phases that will be used. This feature allows the designer to select the number of phases required for a particular application. Six-phase operation is standard. All phases switch with a 60 degree delay between pulses. No special connections are required. Five-phase operation is achieved by disabling either phase 3 or phase 6. Tie together CS3N and CS3P or CS6N and CS6P, and then pull both pins to VCC. The remaining phases will continue to switch, but now there will be a 72 degree delay between pulses. The phase firing order will become 1-2-3-4-5 or 1-2-4-5-6, depending on which phase was disabled. Four-phase operation is achieved by tying together CS3N, CS3P, CS6N and CS6P, and pulling all of these pins to VCC. This will result in a 90 degree phase delay, and a firing order of 1-2-4-5. Three-phase operation may be realized as well. First, the designer must choose the proper phases. For example, for three-phase operation, phases 2, 4 and 6 must be selected. Second, the current sense inputs should be pulled to a defined voltage ground. Simply tie all the current sense inputs of the unused phases together and connect them to ground. Design Procedure
1. Setting the Switching Frequency
The output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. Typically, microprocessor applications require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. The bulk capacitors provide "hold up" during transient loading. The low impedance capacitors reduce steady-state ripple and bypass the bulk capacitance when the output current changes very quickly. The microprocessor manufacturers usually specify a minimum number of ceramic capacitors. The designer must determine the number of bulk capacitors. Choose the number of bulk output capacitors to meet the peak transient requirements. The formula below can be used to provide a starting point for the minimum number of bulk capacitors (NOUT,MIN):
DI NOUT,MIN + ESR per capacitor @ O,MAX DVO,MAX
(1)
In reality, both the ESR and ESL of the bulk capacitors determine the voltage change during a load transient according to:
DVO,MAX + (DIO,MAX Dt) @ ESL ) DIO,MAX @ ESR (2)
The per-phase switching frequency is set by placing a resistor from ROSC to GND. Choose the resistor according to Figure 6.
Unfortunately, capacitor manufacturers do not specify the ESL of their components and the inductance added by the PCB traces is highly dependent on the layout and routing. Therefore, it is necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors.
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NCP5316
The latest Intel processor specifications discuss "dynamic VID" (DVID), in which the VID codes are stepped up or down to a new desired output voltage. Due to the timing requirements at which the output must be in regulation, the output capacitor selection becomes more complicated. The ideal output capacitor selection has low ESR and low capacitance. Too much output capacitance will make it difficult to meet DVID timing specifications; too much ESR will complicate the transient solution. The Sanyo 4SEPC560 and Panasonic EEU-FL provide a good balance of capacitance vs. ESR.
3. Output Inductor Selection
The maximum inductor value is limited by the transient response of the converter. If the converter is to have a fast transient response, the inductor should be made as small as possible. If the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required and the converter cost will be increased. For a given inductor value, it is useful to determine the times required to increase or decrease the current. For increasing current:
DtINC + Lo @ DIO (VIN * VOUT)
(3.1)
The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady-state and transient performance of the converter. When selecting an inductor, the designer must consider factors such as DC current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size and cost (usually the primary concern). In general, the output inductance value should be electrically and physically as small as possible to provide the best transient response at minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, too low an inductance value will result in very large ripple currents in the power components (MOSFETs, capacitors, etc.) resulting in increased dissipation and lower converter efficiency. Increased ripple currents force the designer to use higher rated MOSFETs, oversize the thermal solution, and use more, higher rated input and output capacitors, adversely affecting converter cost. One method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. Lower ripple currents will result in less core and MOSFET losses and higher converter efficiency. Equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current (a) per phase. The inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. Conversely, higher inductor values will result in less than the selected maximum ripple current.
(VIN * VOUT) @ VOUT LoMIN + (a @ IO,MAX @ VIN @ fSW)
(3)
For decreasing current:
DtDEC + Lo @ DIO (VOUT)
(3.2)
For typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. Thus, it may be more difficult for the converter to stay within the regulation limits when the load is removed than when it is applied and excessive overshoot may result. The output voltage ripple can be calculated using the output inductor value derived in this Section (LoMIN), the number of output capacitors (NOUT,MIN) and the per capacitor ESR determined in the previous Section:
VOUT,P-P + (ESR per cap NOUT,MIN) @ (VIN * #Phases @ VOUT) @ D (LoMIN @ fSW)
(4)
This formula assumes steady-state conditions with no more than one phase on at any time. The second term in Equation 4 is the total ripple current seen by the output capacitors. The total output ripple current is the "time summation" of the four individual phase currents that are 90 degrees out-of-phase. As the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. Therefore, the total output ripple current and voltage are reduced in a multi-phase converter.
4. Input Capacitor Selection
a is the ripple current as a percentage of the maximum output current per phase (a = 0.15 for 15%, a= 0.25 for 25%, etc.). If the minimum inductor value is used, the inductor current will swing a% about its value at the center. Therefore, for a four-phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + a) IO,MAX/4.
The choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. The designer must choose capacitors that will support the worst case input voltage with adequate margin. To calculate the number of input capacitors, one must first determine the total RMS input ripple current. To this end, begin by calculating the average input current to the converter:
IIN,AVG + IO,MAX @ D h
(5)
where: D is the duty cycle of the converter, D = VOUT/VIN; h is the specified minimum efficiency; IO,MAX is the maximum converter output current.
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The input capacitors will discharge when the control FET is ON and charge when the control FET is OFF as shown in Figure 23.
IC,MAX IC,MIN 0A DIC,IN = IC,MAX - IC,MIN
In general, capacitor manufacturers require derating to the specified ripple-current based on the ambient temperature. More capacitors will be required because of the current derating. The designer should know the ESR of the input capacitors. The input capacitor power loss can be calculated from:
PCIN + ICIN,RMS2 @ ESR_per_capacitor NIN (13)
tON FET Off, Caps Charging
T/4
-IIN,AVG
Low ESR capacitors are recommended to minimize losses and reduce capacitor heating. The life of an electrolytic capacitor is reduced 50% for every 10C rise in the capacitor's temperature.
5. Input Inductor Selection
FET On, Caps Discharging
Figure 23. Input Capacitor Current for a Four-Phase Converter
The following equations will determine the maximum and minimum currents delivered by the input capacitors:
IC,MAX + ILo,MAX h * IIN,AVG IC,MIN + ILo,MIN h * IIN,AVG
(6) (7)
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAX f ) DILo 2
(8)
where f is the number of phases in operation. ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX f * DILo 2
(9)
DILo is the peak-to-peak ripple current in the output inductor of value Lo:
DILo + (VIN * VOUT) @ D (Lo @ fSW)
(10)
For the four-phase converter, the input capacitor(s) RMS current is then:
ICIN,RMS + [4D @ (IC,MIN2 ) IC,MIN @ DIC,IN
(11)
The use of an inductor between the input capacitors and the power source will accomplish two objectives. First, it will isolate the voltage source and the system from the noise generated in the switching supply. Second, it will limit the inrush current into the input capacitors at power up. Large inrush currents reduce the expected life of the input capacitors. The inductor's limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case input current slew rate will occur during the first few PWM cycles immediately after a step-load change is applied as shown in Figure 24. When the load is applied, the output voltage is pulled down very quickly. Current through the output inductors will not change instantaneously, so the initial transient load current must be conducted by the output capacitors. The output voltage will step downward depending on the magnitude of the output current (IO,MAX), the per capacitor ESR of the output capacitors (ESROUT) and the number of the output capacitors (NOUT) as shown in Figure 24. Assuming the load current is shared equally between all phases, the output voltage at full transient load will be:
VOUT,FULL-LOAD +
(14)
VOUT,NO-LOAD * (IO,MAX f) @ ESROUT NOUT
) DIC,IN2 3) ) IIN,AVG2 @ (1 * 4D)]1 2
Select the number of input capacitors (NIN) to provide the RMS input current (ICIN,RMS) based on the RMS ripple current rating per capacitor (IRMS,RATED):
NIN + ICIN,RMS IRMS,RATED
(12)
When the control MOSFET (Q1 in Figure 24) turns ON, the input voltage will be applied to the opposite terminal of the output inductor (the SWNODE). At that instant, the voltage across the output inductor can be calculated as:
DVLo + VIN * VOUT,FULL-LOAD + VIN * VOUT,NO-LOAD ) (IO,MAX f) @ ESROUT NOUT
(15)
For a four-phase converter with perfect efficiency (h = 1), the worst case input ripple-current will occur when the converter is operating at a 12.5% duty cycle. At this operating point, the parallel combination of input capacitors must support an RMS ripple current equal to 12.5% of the converter's DC output current. At other duty cycles, the ripple-current will be less. For example, at a duty cycle of either 6% or 19%, the four-phase input ripple-current will be approximately 10% of the converter's DC output current.
The differential voltage across the output inductor will cause its current to increase linearly with time. The slew rate of this current can be calculated from:
dILo dt + DVLo Lo
(16)
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NCP5316
MAX dI/dt occurs in first few PWM cycles. ILi Li 470 nH NCi x Ci + Vi - 12 V ESRCi/NCi Vi(t = 0) = 12 V Q1 SWNODE ILo Lo
+ VCi +
VOUT
Vo(t = 0) = 1.480 V
NCo x Co 60 u(t)
Q2
ESRCo/NCo
Figure 24. Calculating the Input Inductance
Current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. The amount of voltage drop across the input capacitors (DVCi) is determined by the number of input capacitors (NIN), their per capacitor ESR (ESRIN) and the current in the output inductor according to:
(17)
6. MOSFET & Heatsink Selection
DVCi + ESRIN NIN dl @ Lo dt @ D fSW
Before the load is applied, the voltage across the input inductor (VLi) is very small and the input capacitors charge to the input voltage VIN. After the load is applied, the voltage drop across the input capacitors, DVCi, appears across the input inductor as well. Knowing this, the minimum value of the input inductor can be calculated from:
LiMIN + VLi + DVCi dIIN dtMAX dIIN dtMAX
(18)
Power dissipation, package size and thermal requirements drive MOSFET selection. To adequately size the heat sink, the design must first predict the MOSFET power dissipation. Once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or upper MOSFET will display both switching and conduction losses. The synchronous or lower MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non-overlap time of the gate drivers. For the upper or control MOSFET, the power dissipation can be approximated from:
PD,CONTROL + (IRMS,CNTL2 @ RDS(on)) ) (ILo,MAX @ Qswitch Ig @ VIN @ fSW) ) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
(19)
dIIN/dtMAX is the maximum allowable input current slew rate. The input inductance value calculated from Equation 18 is relatively conservative. It assumes the supply voltage is very "stiff" and does not account for any parasitic elements that will limit dI/dt such as stray inductance. Also, the ESR values of the capacitors specified by the manufacturer's data sheets are worst case high limits. In reality, input voltage "sag," lower capacitor ESRs and stray inductance will help reduce the slew rate of the input current. As with the output inductor, the input inductor must support the maximum current without saturating the inductor. Also, for an inexpensive iron powder core, such as the -26 or -52 from Micrometals, the inductance "swing" with DC bias must be taken into account and inductance will decrease as the DC input current increases. At the maximum input current, the inductance must not decrease below the minimum value or the dI/dt will be higher than expected.
The first term represents the conduction or IR losses when the MOSFET is ON while the second term represents the switching losses. The third term is the loss associated with the control and synchronous MOSFET output charge when the control MOSFET turns ON. The output losses are caused by both the control and synchronous MOSFET but are dissipated only in the control FET. The fourth term is the loss due to the reverse recovery time of the body diode in the synchronous MOSFET. The first two terms are usually adequate to predict the majority of the losses.
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NCP5316
IRMS,CNTL is the RMS value of the trapezoidal current in the control MOSFET:
IRMS,CNTL + D
(20)
ID
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAX f ) DILo 2
(21) VGS_TH (22) QGS1 (23) QGS2 QGD
VGATE
ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX f * DILo 2
IO,MAX is the maximum converter output current. D is the duty cycle of the converter:
D + VOUT VIN
VDRAIN
Figure 25. MOSFET Switching Characteristics
DILo is the peak-to-peak ripple current in the output inductor of value Lo:
DILo + (VIN * VOUT) @ D (Lo @ fSW)
(24)
RDS(on) is the ON resistance of the MOSFET at the applied gate drive voltage. Qswitch is the post gate threshold portion of the gate-to-source charge plus the gate-to-drain charge. This may be specified in the data sheet or approximated from the gate-charge curve as shown in the Figure 25.
Qswitch + Qgs2 ) Qgd
(25)
When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature.
qT t (TJ * TA) PD
(28)
Ig is the output current from the gate driver IC. VIN is the input voltage to the converter. fsw is the switching frequency of the converter. QG is the MOSFET total gate charge to obtain RDS(on); commonly specified in the data sheet. Vg is the gate drive voltage. QRR is the reverse recovery charge of the lower MOSFET. Qoss is the MOSFET output charge specified in the data sheet. For the lower or synchronous MOSFET, the power dissipation can be approximated from:
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on)) ) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW)
(26)
where: qT is the total thermal impedance (qJC + qSA); qJC is the junction-to-case thermal impedance of the MOSFET; qSA is the sink-to-ambient thermal impedance of the heatsink assuming direct mounting of the MOSFET (no thermal "pad" is used); TJ is the specified maximum allowed junction temperature; TA is the worst case ambient operating temperature. For TO-220 and TO-263 packages, standard FR-4 copper clad circuit boards will have approximate thermal resistances (qSA) as shown below:
Pad Size (in2/mm2) 0.50/323 0.75/484 1.00/645 1.50/968 Single-Sided 1 oz. Copper 60-65C/W 55-60C/W 50-55C/W 45-50C/W
where: Vfdiode is the forward voltage of the MOSFET's intrinsic diode at the converter output current. t_nonoverlap is the non-overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the data sheet for the control IC. The first term represents the conduction or IR losses when the MOSFET is ON and the second term represents the diode losses that occur during the gate non-overlap time. All terms were defined in the previous discussion for the control MOSFET with the exception of:
IRMS,SYNCH + 1 * D
(27)
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading and component variations (i.e., worst case MOSFET RDS(on)). Also, the inductors and capacitors share the MOSFET's heatsinks and will add heat and raise the temperature of the circuit board and MOSFET. For any new design, it is advisable to have as much heatsink area as possible. All too often, new designs are found to be too hot and require re-design to add heatsinking.
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NCP5316
RCS1 L1 0A CS1P +- - + - + 10 + S - GVDRP COMP VID - 20 mV
CCS1 CS1N RCSx CSxP
Error Amp RDRP
RFB VCORE
Lx 0A
CCSx CSxN
+ - GVDRP
VDRP = VID
VFB = VID - 20 mV
IDRP = 0
IFB = 0
VCORE = VID + IBIASVFB w RFB
Figure 26. AVP Circuitry at No-Load
RCS1 L1 IMAX/2 +- + S - GVDRP COMP VID - 20 mV
CS1P
CCS1
CS1N CSxP
Error Amp RDRP
RCSx Lx IMAX/n
RFB
+ - GVDRP
VDRP = VID + VFB = VID - 20 mV VCORE IMAX * RL * GVDRP IDRP IFB
CCSx
CSxN
IDRP = IMAX * RL * GVDRP/RDRP IFBK = IDRP VCORE = VID - IDRP w RFB = VID - IMAX w RL w GVDRP w RFB/RDRP
Figure 27. AVP Circuitry at Full-Load 7. Adaptive Voltage Positioning
Two resistors program the Adaptive Voltage Positioning (AVP): RFB and RDRP. These components form a resistor divider, shown in Figures 26 and 27, between VDRP, VFB, and VOUT. Resistor RFB is connected between VOUT and the VFB pin of the controller. At no load, this resistor will conduct the very small internal bias current of the VFB pin. Therefore VFB should be kept below 10 kW to avoid output voltage error due to the input bias current. If the RFB resistor is kept small, the VFB bias current can be ignored. Resistor RDRP is connected between the VDRP and VFB pins of the controller. At no load, these pins should be at an equal potential, and no current should flow through RDRP. In reality, the bias current coming out of the VDRP pin is likely to have a small positive voltage with respect to VFB. This current produces a small decrease in output voltage at no load, which can be minimized by keeping the RDRP resistor below 30 kW. As load current increases, the voltage at the VDRP pin rises. The ratio of the RDRP and RFB resistors
causes the voltage at the VFB pin to rise, reducing the output voltage. Figure 28 shows the DC effect of AVP, given an appropriate resistor ratio.
0 -0.02 -0.04 VOUT (V) -0.06 -0.08 -0.10 -0.12 -0.14 0 20 30 IOUT (A) 40 50 60 Spec Min Spec Max VID - VOUT
Figure 28. The DC Effects of AVP vs. Load
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NCP5316
Figure 29. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Long (Slow): VDRP and VOUT Respond Too Slowly.
Figure 30. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Short (Fast): VDRP and VOUT Both Overshoot. RCSx @ CCSx + Lo (Rsense)
(31)
To choose components, recall that the two resistors RFB and RDRP form a voltage divider. Select the appropriate resistor ratio to achieve the desired loadline. At no load, the output voltage is positioned 20 mV below the DAC output setting. The output voltage droop will follow the equation:
RR RDRP + g @ L FB RLL
(29)
where: g = gain of the current sense amplifiers (V/V); RSENSE = resistance of the sense element (mW); RLL = load line resistance (mW). It is easiest to select a value for RFB and then evaluate the equation to find RDRP. RLL is simply the desired output voltage droop divided by the output current. If a sense resistor is used to detect inductor current, then RSENSE will be the value of the sense resistor. If inductor sensing is used, RSENSE will be the resistance of the inductor, assuming that the current sense network equation (eq. 30) is valid. Refer to the discussion on Current Sensing for further information.
8. Current Sensing
Figure 31. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Optimal: VDRP and VOUT Respond to the Load Current Quickly Without Overshooting.
Current sensing is used to balance current between different phases, to limit the maximum phase current and to limit the maximum system current. Since the current information, sensed across the inductor, is a part of the control loop, better stability is achieved if the current information is accurate and noise-free. The NCP5316 introduces a novel feature to achieve the best possible performance: differential current sense amplifiers. Two sense lines are routed for each phase, as shown in Figure 27. For inductive current sensing, choose the current sense network (RCSx, CCSx, x = 1, 2, 3, 4, 5 or 6) to satisfy
RCSx @ CCSx + Lo (RL ) RPCB)
(30)
This will provide an adequate starting point for RCSx and CCSx. After the converter is constructed, the value of RCSx (and/or CCSx) should be fine-tuned in the lab by observing the VDRP signal during a step change in load current. Tune the RCSx CCSx network by varying RCSx to provide a "square-wave" at the VDRP output pin with maximum rise time and minimal overshoot as shown in Figure 31.
9. Error Amplifier Tuning
For resistive current sensing, choose the current sense network (RCSx, CCSx, x = 1, 2, 3, 4, 5 or 6) to satisfy
After the steady-state (static) AVP has been set and the current sense network has been optimized, the Error Amplifier must be tuned. The gain of the Error Amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the Error Amplifier's feedback capacitor (CAMP). The bandwidth of the control loop will vary directly with the gain of the error amplifier.
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NCP5316
If CAMP is too large, the loop gain/bandwidth will be low, the COMP pin will slew too slowly and the output voltage will overshoot as shown in Figure 32. On the other hand, if CAMP is too small, the loop gain/bandwidth will be high, the COMP pin will slew very quickly and overshoot will occur. Integrator "wind up" is the cause of the overshoot. In this case, the output voltage will transition more slowly because COMP spikes upward as shown in Figure 33. Too much loop gain/bandwidth increases the risk of instability. In general, one should use the lowest loop gain/bandwidth possible to achieve acceptable transient response. This will insure good stability. If CAMP is optimal, the COMP pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in Figure 35. After the control loop is tuned to provide an acceptable transient response, the steady-state voltage ripple on the COMP pin should be examined. When the converter is operating at full steady-state load, the peak-to-peak voltage ripple (VPP) on the COMP pin should be less than 20 mVPP as shown in Figure 34. Less than 10 mVPP is ideal. Excessive ripple on the COMP pin will contribute to jitter.
Figure 33. The Value of CAMP Is Too Low and the Loop Gain/Bandwidth Too High. COMP Moves Too Quickly, Which Is Evident from the Small Spike in Its Voltage When the Load Is Applied or Removed. The Output Voltage Transitions More Slowly Because of the COMP Spike.
Figure 32. The Value of CAMP Is Too High and the Loop Gain/Bandwidth Too Low. COMP Slews Too Slowly Which Results in Overshoot in VOUT.
Figure 34. At Full-Load the Peak-to-Peak Voltage Ripple on the COMP Pin Should Be Less than 20 mV for a Well-Tuned/Stable Controller. Higher COMP Voltage Ripple Will Contribute to Output Voltage Jitter.
Figure 35. The Value of CAMP Is Optimal. COMP Slews Quickly Without Spiking or Ringing. VOUT Does Not Overshoot and Monotonically Settles to Its Final Value.
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NCP5316
10. Current Limit Setting
When the output of the current sense amplifier (COx in the block diagram) exceeds the voltage on the ILIM pin, the part will latch off. For inductive sensing, the ILIM pin voltage should be set based on the inductor's maximum resistance (RLMAX). The design must consider the inductor's resistance increase due to current heating and ambient temperature rise. Also, depending on the current sense points, the circuit board may add additional resistance. In general, the temperature coefficient of copper is +0.39% per C. If using a current sense resistor (RSENSE), the ILIM pin voltage should be set based on the maximum value of the sense resistor. Since under transient conditions, a single phase may see a very high positive or negative current for mere microseconds at a time, the user may set a limit to the maximum phase current. The phase current limit prevents an individual phase from conducting too much current in either the positive or negative direction. The IPLIM pin is used to set this threshold. The IO pin provides an output signal proportional to inductor current, which can be used for system validation purposes as well as for current limiting. This signal is fed back into the IC through a low-pass filter between IO and IOF, as shown in Figure 36, so designers may customize the response time of the current limit functions.
IO RIO IOF CIO
VIO can be calculated as
VIO + nF @ IL @ RL @ g @ 3.3
where: nF = the number of phases; IL = inductor current (A); RL = sense element resistance (W); g = current sense to IO pin gain. The user may easily set the phase and module current limits at this point. This limit is programmed by a resistor divider from VREF, as shown in Figure 37.
VREF R1 ILIM R2 R4 R3 IPLIM
Figure 37. Programming the Current Limits
When the NCP5316 is powered up, VREF will be 3.3 V. This allows the user to set the module and phase current limits with the resistor divider shown above.
Module Current Limit + VREF R1 @ RL @ g @ nF R1 ) R2 VREF R3 @ 9.5 @ RL R3 ) R4
Phase Current Limit +
Figure 36. Filtering the IO Signal
The designer should select these values empirically. A 0.01 mF capacitor and a 20 kW resistor will prevent inadvertent current limit triggering in many cases.
For convenience in component selection, as well as to keep the VREF pin current below 1 mA, the designer is recommended to set R2 and R4 equal to 10 kW. For the overcurrent protection to work properly, the current sense time constant (RC) should be slightly larger than the RL time constant. If the RC time constant is too fast, a step load change will cause the sensed current waveform to appear larger than the actual inductor current and will trip the current limit at a lower level than expected.
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NCP5316
PACKAGE DIMENSIONS
48-PIN QFN, 7 y 7 MN SUFFIX CASE 485K-02 ISSUE B
-X- A -Y-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.30 AND 0.35 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. 485K-01 OBSOLETE, NEW STANDARD IS 485K-02. DIM A B C D E F G J K L M N R P MILLIMETERS MIN MAX 7.00 BSC 7.00 BSC 0.80 1.00 0.23 0.28 5.26 5.46 5.26 5.46 0.50 BSC 0.20 REF 0.00 0.05 0.35 0.45 2.85 2.95 2.85 2.95 0.60 0.80 0.42 REF INCHES MIN MAX 0.276 BSC 0.276 BSC 0.031 0.039 0.009 0.011 0.207 0.215 0.207 0.215 0.020 BSC 0.008 REF 0.000 0.002 0.014 0.018 0.112 0.116 0.112 0.116 0.024 0.031 0.165 REF
B
2 PL
0.15 (0.006) T
2 PL
0.15 (0.006) T TOP VIEW J R 0.08 (0.0031) T SIDE VIEW E L M
13 12 24 25 EXPOSED PAD
0.10 (0.004) T K
C -T-
SEATING PLANE
48 PL
P
4 PL
F N
1 48 D 48 PL NOTE 3 37 36
G
0.10 (0.004)
M
TXY BOTTOM VIEW
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NCP5316
PACKAGE DIMENSIONS
LQFP-48 FTB SUFFIX CASE 932-02 ISSUE E
4X
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA MILLIMETERS MAX MIN 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 1_ 5_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AC
BASE METAL
AD M_
TOP & BOTTOM
R
GAUGE PLANE
SECTION AE-AE
EEE CCCC EEE CCCC CCCC
F D 0.080
M
C
E
AC T-U Z H W DETAIL AD AA K L_
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0.250
N
J
NCP5316
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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